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MA5114
MA5114
Radiation hard 1024x4 Bit Static RAM
Replaces June 1999 version, DS3591-4.0 DS3591-5.0 January 2000
The MA5114 4k Static RAM is configured as 1024 x 4 bits and manufactured using CMOS-SOS high performance, radiation hard, 3m technology. The design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. Address input buffers are deselected when Chip Select is in the HIGH state. Operation Mode Read Write Standby CS L L H WE H L X I/O D OUT D IN High Z ISB2 Power ISB1
FEATURES
s 3m CMOS-SOS Technology s Latch-up Free s Fast Access Time 90ns Typical s Total Dose 106 Rad(Si) s Transient Upset >1010 Rad(Si)/sec s SEU <10-10 Errors/bitday s Single 5V Supply s Three State Output s Low Standby Current 50A Typical s -55C to +125C Operation s All Inputs and Outputs Fully TTL or CMOS Compatible s Fully Static Operation s Data Retention at 2V Supply
Figure 1: Truth Table
Figure 2: Block Diagram
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MA5114
CHARACTERISTICS AND RATINGS
Symbol VCC VI TA TS Parameter Supply Voltage Input Voltage Operating Temperature Storage Temperature Min. -0.5 -0.3 -55 -65 Max. 7 VDD+0.3 125 150 Units V V C C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5: 1. Characteristics apply to pre radiation at TA = -55C to +125C with VDD = 5V 10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10% (characteristics at higher radiation levels available on request). 2. Worst case at TA = +125C, guaranteed but not tested at TA = -55C. GROUP A SUBGROUPS 1, 2, 3. Symbol VDD VlH VlL VOH VOL ILI ILO IPUI IPDI IDD ISB1 ISB2 Parameter Supply voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current (note 2) Output Leakage Current (note 2) Input Pull-Up Current Input Leakage Current Power Supply Current Selected Supply Current Standby Supply Current Conditions IOH1 = -1mA IOL = 2mA All inputs except CS Output disabled, VOUT = VSS or VDD VIN = VSS on CS input only VIN = VSS on CS input only fRC = 1MHz, CS = 50% mark:spaceCS = VSS Chip disabled Min. 4.5 VDD/2 VSS 2.4 12 Typ. 5.0 16 25 50 Max. 5.5 VDD 0.8 0.4 10 20 -100 5 mA 35 3000 mA A Units V V V V V A A A A
Figure 4: Electrical Characteristics
Symbol VDR IDDR
Parameter VCC for Data Retention Data Retention Current
Conditions CS = VDR CS = VDR, VDR = 2.0V
Min. 2.0 -
Typ. 30
Max. 2000
Units V A
Figure 5: Data Retention Characteristics
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MA5114
AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6: 1. Input pulse = VSS to 3.0V. 2. Times measurement reference level = 1.5V. 3. Transition is measured at 500mV from steady state. 4. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7: Characteristics apply to pre-radiation at TA = -55C to +125C with VDD = 5V10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10%. GROUP A SUBGROUPS 9, 10, 11. Symbol TAVAVR TAVQV TELQV TELQX (3,4) TELQZ (3,4) TAXQX Parameter Read Cycle Time Address Access Time Chip Select to Output Valid Chip Select to Output Active Chip Select to Output Tri State Output Hold from Address Change Min 135 10 10 10 Max 135 135 50 Units ns ns ns ns ns ns
Figure 6: Read Cycle AC Electrical Characteristics
Symbol TAVAVW TAVWL TWLWH TWHAV TDVWH TNHDX TWLQZ (3,4) TELWL TELWH TAVWH TWHQX (3,4)
Parameter Write Cycle Tlme Address Set Up Time Write Pulse Width Write Recovery Time Data Set Up Time Data Hold Time Write Enable to Output Tri State Chip Selection to Write Low Chip Selection to End of Write Address Valid to End of Write Output Active from End to Write
Min 135 10 50 5 35 5 10 25 85 80 5
Max 50 -
Units ns ns ns ns ns ns ns ns ns ns ns
Figure 7: Write Cycle AC Electrical Characteristics
Symbol CIN COUT
Parameter Input Capacitance Output Capacitance
Conditions Vl = 0V VO = 0V
Min. -
Typ. 6 8
Max. 10 12
Units pF pF
Note: TA = 25C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
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MA5114
Symbol FT Parameter Basic Functionality Conditions VDD = 4.5V - 5.5V, FREQ = 1MHz VIL = VSS, VIH = VDD, VOL 1.5V, VOH 1.5V TEMP = -55C to +125C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup 1 2 3 7 8A 8B 9 10 11
Definition Static characteristics specified in Tables 4 and 5 at +25C Static characteristics specified in Tables 4 and 5 at +125C Static characteristics specified in Tables 4 and 5 at -55C Functional characteristics specified in Table 9 at +25C Functional characteristics specified in Table 9 at +125C Functional characteristics specified in Table 9 at -55C Switching characteristics specified in Tables 6 and 7 at +25C Switching characteristics specified in Tables 6 and 7 at +125C Switching characteristics specified in Tables 6 and 7 at -55C
Figure 10: Definition of Subgroups
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MA5114
TIMING DIAGRAMS
TAVAVR ADDRESS TAVQV TELQV CS TELQX
HIGH IMPEDANCE
TAXQX
TEHQZ
DATA OUT
DATA VALID
1. WE is high for Read Cycle. 2. Address Vaild prior to or coincident with CS transition low.
Figure 11a: Read Cycle 1
TAVAVR ADDRESS TAVQV DATA OUT TAXQX
DATA VALID
1. WE is high for Read Cycle. 2. Device is continually selected. CS low.
Figure 11b: Read Cycle 2
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MA5114
TAVAVW
ADDRESS
TAVWH TAVWL
(4)
TWHAV (3) TWLWH (2)
WE
TAXQX TWLQZ TELWL
(7)
TWLQH
(5) (6)
DATA OUT
HIGH IMPEDANCE
TDVWH
DATA IN DATA VALID
TWHDX
TELWH
CS
1. WE must be high during all address transitions. 2. A write occurs during the overlap (TWLWH) of a low CS and a low WE. 3. TWHAV is measured from either CS or WE going high, whichever is the earlier, to the end of the write cycle. 4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in the high impedance state. 5. DATA OUT is in the active state, so DATA IN must not be in opposing state. 6. DATA OUT is the write data of the current cycle, if selected. 7. DATA OUT is the read data of the next address, if selected. 8. TELWL must be met to prevent memory corruption.
Figure 12: Write Cycle
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MA5114
OUTLINES AND PIN ASSIGNMENTS
D
9
1
10
18
W Seating Plane ME
A1 A
H e b Z 15
C e1
Ref A A1 b c D e e1 H Me Z W
Millimetres Min. 0.38 0.35 0.20 4.44 Nom. 2.54 Typ. 8.13 Typ. Max. 5.715 1.53 0.59 0.36 23.11 5.38 8.28 1.27 1.53 Min. 0.015 0.014 0.008 0.175 -
Inches Nom. 0.100 Typ. 0.300 Typ. Max. 0.225 0.060 0.023 0.014 0.910 0.212 0.326 0.050 0.060
A6 A5 A4 A3 A0 A1 A2 CS Vss 1 2 3 4 5 6 7 8 9 Top View 18 Vdd 17 A7 16 A8 15 A9 14 D1 13 D2 12 D3 11 D4 10 WE
XG406
Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C
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MA5114
M b
D
Z
e L A c
ME
A1
Pin 1
Ref A A1 b c D e L M Me Z
Millimetres Min. 0.66 0.38 0.08 14.99 6.73 9.96 7.6 0.13 Nom. 2.54 Max. 3.07 0.48 0.152 15.50 7.75 10.36 1.14 Min. 0.026 0.015 0.003 0.590 0.265 0.392 0.30 0.005
Inches Nom. 0.050 Max. 0.121 0.019 0.006 0.610 0.305 0.408 0.045
XG544
Vdd 24 A7 23 A8 22 A9 21 NC 20 NC 19 D1 18 D2 17 D3 16 D4 15 NC 14 WE 13 Bottom View
1 NC 2 A6 3 A5 4 A4 5 A3 6 NC 7 A0 8 A1 9 A2 10 NC 11 CS 12 Vss
Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F
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MA5114
D
A
e
b
1
NC
A4
A3
A0
A1
8
A5
3 2 1 24 23 22
4
5
6
7
A2
9
10 11
NC CS Vss WE NC D4
Pad 1 Bottom View E
A6 NC Vdd A7 A8
Bottom View
12 13 14
21
20
19
18
17
16 15
NC
NC
D1
D2
Radius r 3 corners
Ref A b1 D E e r
Millimetres Min. 8.76 8.76 Nom. 0.51 1.02 0.19 Max. 2.16 9.14 9.14 Min. 0.345 0.345 -
Inches Nom. 0.020 0.040 0.0075 Max. 0.096 0.360 0.360 -
XG470
Figure 15: 24-Pad Leadless Chip Carrier - Package Style L
D3
A9
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MA5114
P a c k a ge O pt ion Func t ion A6 A5 A4 A3 A0 A1 A2 NCS VSS NWE D4 D3 D2 D1 A9 A8 A7 VDD F 2 3 4 5 7 8 9 11 12 13 15 16 17 18 21 22 23 24 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 L 2 3 4 5 7 8 9 11 12 13 15 16 17 18 21 22 23 24 V ia R R R R R R R R Direct R R R R R R R R Direct S t a t ic 1 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 5V Burnin S t a t ic 2 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V Dy na mic F6 F5 F4 F3 F0 F1 F2 0V 0V 5V LOAD LOAD LOAD LOAD F9 F8 F7 5V Ra dia t ion 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc. 2. Burnin R=1k 3. Radiation R=10k
Figure 16: Burnin and Radiation Configuration
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MA5114
RADIATION TOLERANCE
Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up 1x105 Rad(Si) 5x1010 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 3.4x10-9 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 17: Radiation Hardness Parameters
SINGLE EVENT UPSET CHARACTERISTICS
UPSET BIT CROSS-SECTION (cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 18: Typical Per-Bit Upset Cross-Section vs Ion LET
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MA5114
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance S L C R Radiation Hard Processing 30 kRads (Si) Guaranteed 50 kRads (Si) Guaranteed 100 kRads (Si) Guaranteed
MAx5114xxxxx
QA/QCI Process (See Section 9 Part 4)
Test Process (See Section 9 Part 3) Package Type C F L Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Leadless Chip Carrier Assembly Process (See Section 9 Part 2)
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see `Manufacturing Capability and Quality Assurance Standards' Section 9.
http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com
HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. (c) Dynex Semiconductor 2000 Publication No. DS3581-5 Issue No. 5.0 January 2000 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. No Annotation: The product parameters are fixed and the product is available to datasheet specification.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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